1. Field of the Invention
The present invention relates to an image pick-up device of a multi-channel output system, with the multi channels having a uniform structure.
2. Description of the Related Art
An MOS solid-state image pick-up device adopts a multi-channel output system (multi-line output system) for simultaneously obtaining a plurality of video signal outputs in parallel therewith from a single image pick-up device, as a general method for obtaining a video signal at a high frame rate from an image pick-up device having millions of pixels.
FIG. 1 is an explanatory diagram of a multi-channel output system in a general MOS solid-state pick-up device according to a related art. Referring to FIG. 1, the solid-state pick-up device has (n×n) pixels.
Matrix-arranged pixels P11 to Pnn are divided into four areas. A divided-area-1 has an area ranging from P11 to Paa, a divided-area-2 has an area ranging from P1b to Pan, a divided-area-3 has an area ranging from Pb1 to Pna, and a divided-area-4 has an area ranging from Pbb to Pnn.
A vertical scanning circuit 5 drives pixels on first to a-th rows, and a vertical scanning circuit 6 drives pixels on b-th to n-th rows. Horizontal reading circuits 1 and 3 read pixels on first to a-th columns, and horizontal reading circuits 2 and 4 read pixels on b-th to n-th columns.
Signal outputs are obtained from the pixels arranged in the respective divided-area-1 to divided-area-4, that is, the signal outputs from the pixels P11 to Paa in the divided-area-1 are obtained by the horizontal reading circuit (also referred to as a horizontal scanning circuit) 1 and the vertical scanning circuit 5. The signal outputs from the pixels P1b to Pan in the divided-area-2 are obtained by the horizontal reading circuit 2 and the vertical scanning circuit 5. The signal outputs from the pixels Pb1 to Pna in the divided-area-3 are obtained by the horizontal reading circuit 3 and the vertical scanning circuit 6. The signal outputs from the pixels Pbb to Pnn in the divided-area-4 are obtained by the horizontal reading circuit 4 and the vertical scanning circuit 6.
FIG. 2 shows an image pick-up device for processing a plurality of video signal outputs as obtained as above according to the related art. The signals from the horizontal reading circuits 1 to 4 are supplied respectively to signal processing units 7 to 10. The signal processing units 7 to 10 have the same structure and comprise an amplifier and an AD converter, respectively. In the signal processing units 7 to 10, the respective input signals are amplified by the amplifiers, the amplified signals are converted into digital signals by the AD converters, and the digital signals are then supplied to an image memory 11. The image memory 11 stores and holds the signals from the signal processing units 7 to 10, and supplies the stored signals to a video signal processing unit (not shown) at the latter stage. The image memory 11 combines pixel signals in the divided-area-1 to divided-area-4, thus to form one image.
By the way, in the device with the above structure, the video signals in each of the divided-area-1 to divided-area-4 pass through signal processing systems individually comprising a scanning circuit and a video signal processing unit. Thus, the differences of electric properties among the signal processing systems cause the variation in signal level. Consequently, the quality of the finally-combined image degrades.
Then, Japanese Unexamined Patent Application Publication No. 2000-209503 (Patent Document 1) discloses the suggestion to solve the above-mentioned problem.
FIG. 3 is an explanatory diagram showing an image pick-up device disclosed in Japanese Unexamined Patent Application Publication No. 2000-209503 (Patent Document 1). The image pick-up device shown in FIG. 3 is a general MOS solid-state pick-up device.
The pixel arrangement of the image pick-up device shown in FIG. 3 is the same as that shown in FIG. 1. In the image pick-up device shown in FIG. 1, the pixels are included in one of the divided areas. However, the divided areas do not include any common pixel. On the contrary, in the image pick-up device shown in FIG. 3, the adjacent divided areas include common pixels. That is, in the example shown in FIG. 3, a divided-area-1 comprises pixels P11 to Pbb, a divided-area-2 comprises pixels P1a to Pbn, a divided-area-3 comprises pixels Pa1 to Pnb, and a divided-area-4 comprises pixels Paa to Pan.
Horizontal reading circuits 15 to 18 respectively read the pixels in the divided-area-1 to divided-area-4. For example, the signals of the pixels Paa through Pbb are outputted from the entire horizontal reading circuits 15 to 18. The signals of the pixels Pa1 and Pb1 are outputted from both of the horizontal reading circuits 15 and 17. The outputs from the overlapping-read pixels are averaged, to thus average the property variation in horizontal reading circuits at the boundary of the divided areas and to reduce image deterioration.